As already known, an IGBT or a vertical MOSFET (There are cases in which a MOS structure is a planar type or a trench type), which is a typical example of a power semiconductor device (power device) having a MOS structure, is used, for example, as a switching element in an inverter circuit. This type of power device has a very thin gate insulating film as compared with a field oxide film or the like.
Here, a vertical power MOSFET described in Patent Document 1 is a device using Si as a semiconductor substrate material. As illustrated in FIGS. 1 and 2 in Patent Document 1, in an adjacent region on a side of a cell region of a MOSFET adjacent to a periphery of the cell region of the MOSFET (including a gate pad), minute diodes are arranged at least in one row along the periphery. Each of such diodes arranged in one row in the region between the gate pad and the cell region of the MOSFET absorbs holes that are injected from a P-well and a P-base into an N-type semiconductor layer on a drain side upon applying a forward bias when the MOSFET is switched from an ON state to an OFF state as illustrated in FIG. 3 of Patent Document 1. For this reason, the structure described in Patent Document 1 can prevent a parasitic transistor illustrated in FIG. 3 of Patent Document 1 from turning on when the MOSFET is switched from a forward bias to a reverse bias. In addition, in the structure described in Patent Document 1, the P-base which is the P-well of a MOSFET cell is electrically connected to a source electrode through a back gate as illustrated in FIG. 2 of Patent Document 1.